1. Field of the Invention
Generally, the present disclosure relates to the formation of integrated circuits, and, more particularly, to techniques for forming transistors having strained channel regions by using embedded strain-inducing semiconductor material to enhance the charge carrier mobility in the channel region of a MOS transistor.
2. Description of the Related Art
The fabrication of integrated circuits requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips and the like, CMOS technology is currently the most promising approach due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of transistors representing the dominant circuit element, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely doped channel region disposed between the drain region and the source region.
The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the majority charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the overall conductivity of the channel region substantially determines the performance of the MOS transistors. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
The continuing shrinkage of the transistor dimensions, however, involves a plurality of issues associated therewith that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. One major problem in this respect is the development of enhanced photolithography and etch strategies so as to reliably and reproducibly create circuit elements of critical dimensions, such as the gate electrode of the transistors, for every new device generation. Moreover, highly sophisticated dopant profiles, in the vertical direction as well as in the lateral direction, are required in the drain and source regions to provide low sheet and contact resistivity in combination with a desired channel controllability. In addition, the vertical location of the PN junctions with respect to the gate insulation layer also represents a critical design criterion in view of leakage current control.
Since the continuous size reduction of the critical dimensions, i.e., the gate length of the transistors, necessitates the adaptation and possibly the new development of highly complex process techniques concerning the above-identified and many other process steps, it has been proposed to also enhance the channel conductivity of the transistor elements by increasing the charge carrier mobility in the channel region for a given channel length, thereby offering the potential for achieving a performance improvement that is comparable with the advance to a future technology node while avoiding or at least postponing many of the above process adaptations associated with device scaling. One efficient mechanism for increasing the charge carrier mobility is the modification of the lattice structure in the channel region, for instance by creating tensile or compressive stress in the vicinity of the channel region to produce a corresponding strain in the channel region, which results in a modified mobility for electrons and holes, respectively. For example, creating tensile strain in the channel region of a silicon layer having a standard crystalline configuration, i.e., a (100) surface orientation with the channel length direction aligned along the <110> direction, increases the mobility of electrons, wherein, depending on the magnitude and direction of the tensile strain, an increase in mobility of 50% or more may be obtained, which, in turn, may directly translate into a corresponding increase in the conductivity. On the other hand, compressive strain in the channel region may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors. The introduction of stress or strain engineering into integrated circuit fabrication is an extremely promising approach for further device generations, since, for example, strained silicon may be considered as a “new” type of semiconductor material, which may enable the fabrication of fast powerful semiconductor devices without requiring expensive semiconductor materials, while many of the well-established manufacturing techniques may still be used.
Consequently, it has been proposed to introduce, for instance, a silicon/germanium layer or a silicon/carbon layer in or below the channel region on the basis of epitaxial growth techniques to create tensile or compressive stress that may result in a corresponding strain. Transistor performance may be considerably enhanced by the introduction of stress-creating layers in or below the channel region, and therefore significant efforts have been made to implement the sequence for forming corresponding stress layers into the conventional and well-approved MOS technique. For instance, the required additional epitaxial growth techniques have been developed and implemented into the process flow to form the germanium- or carbon-containing stress layers at appropriate locations in or below the channel region.
In other approaches, external stress created by, for instance, overlaying layers, spacer elements and the like is used in an attempt to create a desired strain within the channel region. However, the process of creating the strain in the channel region by applying a specified external stress may suffer from an inefficient translation of the external stress into strain in the channel region. Hence, although providing advantages in terms of process complexity over the above-discussed approach requiring additional stress layers within the channel region, the efficiency of the stress transfer mechanism may depend on the process and device specifics and may result in a reduced performance gain for at least one type of transistor.
In another approach, the hole mobility in PMOS transistors is enhanced by forming a strained silicon/germanium layer in the drain and source regions of the transistors, wherein the compressively strained drain and source regions create, for the above standard crystalline conditions, uniaxial strain in the adjacent silicon channel region. To this end, the drain and source regions of the PMOS transistors are selectively recessed, while the NMOS transistors are masked, and subsequently the silicon/germanium layer is selectively formed in the PMOS transistor by epitaxial growth. This technique offers significant advantages in view of performance gain of the PMOS transistor and thus of the entire CMOS device. However, the NMOS transistor may exhibit a reduced performance gain when using a similar technique, for instance on the basis of a silicon/carbon alloy, due to low efficiency of presently available selective epitaxial growth techniques for a silicon/carbon alloy.
Thus, strain engineering by means of embedded semiconductor materials, especially of silicon/germanium, provided as a strained or relaxed layer, depending on the desired effect, has proven to be a powerful means in increasing the device performance of advanced silicon-based transistors. With respect to silicon/germanium material embedded in the drain and source regions, it turns out, however, that the degree of strain induced in the respective channel regions depends on the amount of lattice mismatch between the basic silicon and the embedded semiconductor compound. For silicon/germanium, a maximum concentration of germanium for currently established selective epitaxial growth techniques is limited to approximately 25%, since otherwise germanium conglomeration may occur, which in turn may result in a non-desired stress relief in the corresponding embedded semiconductor compound material, thereby also reducing the strain in the respective channel region. Furthermore, the selective epitaxial growth techniques for forming strained silicon/germanium materials in the drain and source regions of P-channel transistors may result in an asymmetry with respect to performance gain in P-channel transistors and N-channel transistors.
The present disclosure is directed to various techniques and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.